A Design Technique for Faster Dadda Multiplier

AbstractIn this work faster column compression multiplication has been achieved by using a combination of two design techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using a hybrid adder proposed in this work. Based on the proposed techniques 8, 16, 32 and 64bit Dadda multipliers are developed and compared with the regular Dadda multiplier. The performance of the proposed multiplier is analyzed by evaluating the delay, area and power, with 180 nm process technologies on interconnect and layout using industry standard design and layout tools. The result analysis shows that the 64-bit regular Dadda multiplier is as much as 41.1% slower than the proposed multiplier and requires only 1.4% and 3.7% less area and power respectively. Also the power-delay product of the proposed design is significantly lower than that of the regular Dadda multiplier.